Silicon Engineering Manager, EMIR and Power Grid, AI/ML
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Minimum qualifications:
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
- 10 years of technical experience in physical design disciplines involving power delivery and advanced process technology nodes.
- 3 years of experience in people management, developing employees.
- Experience with power grid integrity (EMIR) from initial budgeting to analysis, verification, and final signoff.
- Experience using standard EMIR tools like RedHawk, Totem, and Voltus, establishing EMIR budgets, defining signoff methodologies, and bringing up flows for new projects.
- Experience with power grid design and related design trade-offs.
Preferred qualifications:
- Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
- Experience owning EMIR at the block or full-chip level, including proactive floorplanning and defining standard cell usage with physical design owners.
- Experience with power delivery voltage droop mitigation.
- Knowledge of semiconductor project life cycle and quality goals of all functions.
- Familiarity with low power design techniques (e.g., multi Vth/power/voltage domain design, clock gating, power gating, Dynamic Voltage Frequency Scaling).
About the job
In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.
As a Silicon Engineering Manager, you will directly manage and drive the team collaborating with physical design, circuits, technology, and package leads to overcome the slowing of Moore’s Law in advanced technology nodes and deliver ASICs and SoCs. You will drive competitive and reliable products by optimizing, analyzing, customizing, and verifying our power delivery network to meet performance and integrity specifications. You will manage technical evaluations of EDA tools, process nodes, and IPs and provide recommendations. You will develop new and novel power delivery and reliability solutions and methodologies that co-optimize across the entire design space, then see these through from inception to maturity and tapeout.
The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.
We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.
Individual pay is determined by factors including job-related skills, experience, and relevant education or training.US: $192000 - $278000 (USD) + 20% bonus target + equity + benefits
Learn more about benefits at Google.
Responsibilities
- Direct, manage, and set strategy for the power grid distribution and power integrity team, accurately identifying required skills and allocating resources across all active projects.
- Manage the evaluates electromigration (EM) and voltage drops (IR drop) (EMIR) team to complete analysis at the block, sub-chip, and full-chip levels, successfully executing comprehensive signoff checks to ensure highly robust final design reliability.
- Collaborate closely with physical design, STA, package, and circuit teams to define EMIR budgets, signoff methodologies, and proactive mitigation strategies like optimal floorplanning and standard cell selection.
- Work with internal groups and external software vendors to establish priorities and define critical capabilities for key EMIR tools on projects.
- Own team growth by creating customized development plans, managing staffing initiatives, and fostering a collaborative environment to maximize every member's overall impact and productivity.
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