Silicon Engineer, PhD, University Graduate, 2027 Start
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Minimum qualifications:
- PhD degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
- Experience in any one domain of silicon engineering through internships, academic research, or publications: architecture and RTL, verification and validation, physical design and circuits, systems, test or CAD.
- Experience with one of the hardware description languages (e.g., Verilog, SystemVerilog) or programming (e.g., Python, Tcl, Perl, or C++).
Preferred qualifications:
- Research experience in specialized areas such as high-performance/low-power architectures, domain-specific accelerators (DSAs/TPUs), memory hierarchies, coherent interconnects (e.g., CXL, PCIe, UCIe, NoC), or advanced packaging/chiplets.
- Experience developing and maintaining CAD/EDA design flows, methodology infrastructure, or applying ML for chip design automation.
- Understanding of advanced ML/DL model architectures (e.g., Transformers, LLMs) with experience in performance modeling, cycle-accurate simulation, or custom AI accelerator evaluation.
- Familiarity with industry-standard EDA tools (e.g., from Synopsys, Cadence, Siemens EDA, or emulation/formal platforms).
- Demonstrated research track record and ability to work on complex, open-ended problems, with publications in conferences (e.g., ISCA, MICRO, HPCA, ASPLOS, DAC, ICCAD, ISSCC, NeurIPS, MLSys).
About the job
In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.
The Chip Innovation Infrastructure team focuses on building Google's next-generation systems. The team's work is grounded in creating custom hardware, and as a Silicon Engineer you'll get to collaborate with engineers from various parts of the organization to influence the future of Google Cloud and the AI infrastructure by working on the foundational technology that makes it all possible. This is the hardware that powers everything from Google Cloud, to our most advanced models like Gemini.
The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.
We're the driving team behind Google's groundbreaking innovations, empowering the development of our AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.
Individual pay is determined by factors including job-related skills, experience, and relevant education or training.US: $138000 - $197000 (USD) + 15% bonus target + equity + benefits
Learn more about benefits at Google.
Responsibilities
- Responsibilities and projects will be determined based on your background, interest, and skills.
- Collaborate cross-functionally across hardware and software teams to research, design, and model custom silicon solutions and AI accelerators.
- Develop, simulate, and verify architectural features, digital blocks, or subsystem interfaces targeting performance, power, and area optimizations.
- Contribute to EDA design automation flows, tooling infrastructure, or post-silicon bring-up and characterization.
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