Hardware Emulation Engineer, Google Cloud
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Minimum qualifications:
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
- 1 year of Experience with RTL design (eg Verilog or System Verilog) and simulation (eg VCS or Incisive or Questa).
- 1 year of experience with coding or scripting in C, C++, Perl, TCL or Python.
Preferred qualifications:
- Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
- Experience with emulation systems (ZeBu, Palladium, Veloce), compilation, debug, performance and methodology enhancements.
- Knowledge of external I/O interfaces like PCIe, DDR5, HBM, SPI, or JTAG etc.
About the job
In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.In this role, you will help develop and maintain emulation infrastructure, tools, and workflow methodologies supporting our ASIC projects, as creating ASICs represents a significant investment in time and money. You will have a successful prototyping campaign that helps to ensure success of these critical projects. However, as designs continue to increase in size and complexity, emulation becomes even more important in meeting verification and bring-up milestones. You will provide excellent emulation infrastructure and methodologies that are essential to support these projects.
You will work directly with other emulation team members as well as designers, verification engineers, and software teams. You will interface with our external vendors, lab support teams, networking and security, and EDA tooling and methodology teams to deliver emulation based prototyping capabilities for our ASIC projects. You may also assist in compiling projects targeting our prototyping platforms, debugging issues in both infrastructure and design, and assisting in the hardware and lab bring up and verification of our ASIC systems.The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.
We're behind Google's groundbreaking innovations, empowering the development of AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.Individual pay is determined by factors including job-related skills, experience, and relevant education or training.
US: $116000 - $166000 (USD) + 15% bonus target + bonus + equity + benefits
Learn more about benefits at Google.
Responsibilities
- Maintain and upgrade the emulation infrastructure while serving as a primary interface to emulation vendors.
- Explore emulation methodologies, gather feedback from the team and implement new emulation workflows and methodologies.
- Enable emulation team members in debugging hardware, tooling, and project-specific issues, while supporting software team members in running and debugging tests and performing functional validation on emulation platforms.
- Integrate external interfaces (eg. USB, PCIe, Ethernet etc) on emulation platforms and develop standalone test cases for tool issues encountered in the emulation compile and runtime flows.
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