CPU RTL Design Engineer III
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Minimum qualifications:
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
- 4 years of professional experience in ASIC/SoC digital design using SystemVerilog.
- Experience working on multi-stage, high-performance CPU pipelines and optimizing them for area, power, and timing.
- Experience in logic design through coursework or industry experience.
- Experience with RISC-V architecture and ISA extensions.
- Experience with micro-architecture and RTL design experience in one CPU pipeline stage (e.g., Instruction Fetch Unit (IFU), Decode/Issue/Execution units, or Load-Store Unit (LSU)).
Preferred qualifications:
- Master’s or PhD degree in Electrical Engineering or Computer Science.
- Experience with modern processor microarchitecture and related technologies and algorithms, through academic projects or industry experience.
- Knowledge of programming languages, such as C, C++, and Python.
- Knowledge of general purpose operating systems, such as Linux or Android.
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
As a CPU Micro-architecture and RTL Design Engineer, you will be a key member of the team responsible for enhancing our next-generation RISC-V processor cores. In this role, you will focus on implementing architecture features, including standard or custom RISC-V ISA extensions. You will leverage your deep expertise in CPU pipeline design to optimize and scale our existing core architecture while meeting power, performance, and area (PPA) goals.
The Platforms and Devices team encompasses Google's various computing software platforms across environments (desktop, mobile, applications), as well as our first party devices and services that combine the best of Google AI, software, and hardware. Teams across this area research, design, and develop new technologies to make our user's interaction with computing faster and more seamless, building innovative experiences for our users around the world.
Responsibilities
- Contribute to CPU frontend designs, emphasizing microarchitecture and RTL design for the next-generation CPU.
- Propose efficient, performance-enhancing microarchitecture features, working with architects and performance teams to conduct trade-off studies, communicate their pros and cons, and facilitate final decisions.
- Deliver designs meeting Power, Performance, and Area (PPA) goals with production quality.
- Become familiar with state-of-the-art techniques for at least one processor functional block, and interpret these techniques into design constructs and languages to provide guidance to and participate in the performance modeling effort.
- Work closely with the functional verification team to ensure production quality designs, and with the physical design team to meet frequency, power, and area goals.
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