SoC Silicon Top-Level Floorplan Engineer
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Minimum qualifications:
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
- 8 years of experience in Silicon/ASIC design flows and methodologies.
- 5 years of experience in top level floorplanning/integration roles with multiple levels of hierarchy and assembly.
- Experience planning, owning, and delivering top-level floorplan designs for SoCs in advanced nodes.
- Experience managing cross-functional interactions related to top-level floorplanning of chip projects.
- Experience in SoC Integrated Circuit (IC) design including multi-die partitioning, optimizing performance, power, and area (PPA), and physical verification.
Preferred qualifications:
- Master's degree or PhD in Electrical Engineering, Computer Engineering, or Computer Science with an emphasis on computer architecture.
- Experience in scripting languages (Python, Tcl or Perl) and industry standard top level tools including Innovus, FusionCompiler.
- Experience working on various technologies (embedded processors, DDR, SerDes, HBM, networking-on-chip fabrics, etc.).
- Experience using specialized EDA tools to resolve DRC/LVS/EMIR issues for leading edge nodes.
- Experience with SoC design methodologies for full chip power grid, global clocking, data path implementation, third-party IP integration, and bump planning.
About the job
In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.
In this role, you will be creating the initial physical layout of a chip top-level, defining block sizing/placement, power grids, and clock distribution to meet performance, power, and area (PPA) goals, requiring deep collaboration with architecture, RTL, and synthesis teams, using industry and internal tools, and driving early timing/congestion closure for complex modern SoCs. Your key responsibilities will include full-chip planning, IP integration, delivering floorplan collaterals, and collaborating for signoff. This is a highly cross-functional and central role that will require interactions with numerous development teams.
The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.
We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.
Individual pay is determined by factors including job-related skills, experience, and relevant education or training.US: $163000 - $236000 (USD) + 15% bonus target + equity + benefits
Learn more about benefits at Google.
Responsibilities
- Own the planning, creation and delivery of top-level floorplan deliverables and implementation for Silicon SOC projects from concept to working silicon volume.
- Resolve structural or physical issues related to the integration of complex ASICs and SOCs and collaborate with teams across Google to develop ideas for high impact Silicon and hardware projects.
- Manage all cross-functional interactions related to top-level floorplanning of chip projects.
- Develop and improve floorplan implementation methodologies. Support and execute implementation flows using both industry-standard and specialized internal tools.
- Perform technical evaluations of vendors and IP, providing recommendations and assessment of process node tradeoffs to meet performance, power, area and cost targets.
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